51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
-
+
|
Every PDP-8 instruction is a single 12-bit word, and data are stored in 12-bit core memory locations. All of the PDP-8 registers are 12 bits or smaller.
12 bits lets you address 2¹² = 4096 memory locations, which is why the basic [core memory](https://en.wikipedia.org/wiki/Magnetic-core_memory) size on a PDP-8 is 4 kiW.
# The 3-Level Memory Addressing System
You may be aware that the PDP-8 can be expanded to 32 kiW of memory. How does that square with all of the above?
You may be aware that PDP-8 family computers up through the PDP-8/e can be expanded to a maximum of 32 kiW of core memory. How does that square with all of the above?
In some CPU types, instructions are variable-width, so that an instruction which takes two operands is longer than one that takes a single operand, and a self-contained instruction is shorter still, but in the PDP-8, every instruction takes a single 12-bit word. How can a PDP-8 refer to a 12-bit address when the single-word instructions are 12 bits themselves? And how do we get beyond that to 32 kiW, which would apparently require a 15-bit address? (2¹⁵ words = 32 kiW.)
You may have prior experience with the [16-bit Intel x86 segmentation scheme](https://en.wikipedia.org/wiki/X86#Segmentation). If you thought writing code to deal with that was a pain, buckle up, it gets wild from here.
# Level 1: Pages
|