PiDP-8/I Software

The first FPP peripheral from DEC was the [FPP-12][fpp12]. Although it was introduced with the PDP-12, it is not restricted to the PDP-12: it also works with all of the other PDP-8 family computers contemporaneous with and preceding it, going back to the original PDP-8. This is possible because the FPP is a bus peripheral rather than a feature of the CPU proper. There was also a follow-on peripheral for the PDP-8/a called the [FPP8-A][fpp8a], which is instruction-compatible with the FPP-12. The FPP features of RALF allow you to intermix FPP instructions with PDP-8 instructions just as if the FPP were part of the PDP-8 CPU, rather than being a very different external coprocessor.

Here is a summary of the FPP-related features of RALF:

*   More instructions and pseudo-ops:
    *   Arithmetic: `FADD`, `FADDM`, `FDIV`, `FLDA`, `FMUL`, `FMULM`, `FSTA`, `FSUB`
    *   Set single-word addressing mode base address: `BASE`
    *   Conditional jumps: `JEQ`, `JGE`, `JLE`, `JA`, `JNE`, `JGT`, `JAL`
    *   FPP to PDP-8 jumps: `JXN`, `TRAP3`, `TRAP4`
    *   Indexing: `ADDX`, `INDEX`, `LDX`
    *   Mark module as requiring double-precision hardware: `DPCHK`
    *   No-op: `NOP`
    *   Pointer moves: `JSA`, `JSR`, `SETB`, `SETX`
    *   Processor operations: `FCLA`, `FEXIT`, `FNEG`, `FNORM`, `FPAUSE`, `JAC`, `STARTD`, `STARTF`
    *   Register manipulation: `ALN`, `ATX`, `XTA`
    *   Mark module as requiring double-precision hardware: `DPCHK`
    *   Set single-word addressing mode base address: `BASE`
*   Use 15-bit (double-word) addresses directly in FPP instructions, rather than the [PDP-8's memory model][mm8]

If you see any of those instructions in a PDP-8 assembly language program, it's a pretty good indicator that it's meant to be assembled by RALF or [FLAP](#flap).


#### Relocatable Code

RALF generates relocatable output code in `*.RL` files rather than absolute-addressed output, which means you cannot simply load its output into core and execute it directly. You must use the OS/8 FORTRAN IV loader (`LOAD.SV`) to load one or more `*.RL` files into core memory, link them to any external libraries, convert relative addresses to fixed addresses, and write out a loader image (`*.LD`) which can then be loaded an run by the OS/8 FORTRAN IV Run Time System, `FRTS.SV`.

The compensation for this complicated scheme is that `LOAD.SV` and `FRTS.SV` provide a powerful overlay and linkage loading scheme which allows for programs up to about 300 kWords in size, nearly 10× the maximum core memory size in a standard PDP-8 family computer. It does this by loading code from disk as needed. This scheme is made possible by the relocatable output code from RALF.

(Do not confuse `LOAD.SV`, the OS/8 FORTRAN IV loader — used by both RALF and F4 — with `LOADER.SV`, the simpler "linking loader" used by the OS/8 FORTRAN *II* compiler (`FORT.SV`) and by [SABR](#sabr). There's a second cause for confusion: both loaders use `*.RL` as their default input file name extension, so RALF, F4, FORT, and SABR all output files with that extension.)
(Do not confuse `LOAD.SV`, the OS/8 FORTRAN IV loader — used by both RALF and F4 — with `LOADER.SV`, the simpler "linking loader" used by the OS/8 FORTRAN II compiler (`FORT.SV`) and by [SABR](#sabr). There's a second cause for confusion: both loaders use `*.RL` as their default input file name extension, so RALF, F4, FORT, and SABR all output files with that extension.)


#### Further Improvements

RALF also has many other improvements over late-generation PAL family assemblers such as PAL8 which are not directly tied to driving the FPP or to relocatable code:

*   Expressions: