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12 bits lets you address 2¹² = 4096 memory locations, which is why the basic core memory size on a PDP-8 is 4 kW.⁵
# The 3-Level Memory Addressing System
You may be aware that the PDP-8 can be expanded to 32 kW of memory. How does that square with all of the above?
In some CPU types, instructions are variable-width, so that an instruction which takes two operands is longer than one that takes a single operand, and a self-contained instruction is shorter still, but in the PDP-8, every instruction takes a single 12-bit word. How can a PDP-8 refer to a 12-bit address when the single-word instructions are 12 bits themselves? And how do we get beyond that to 32 kW, which would apparently require a 15-bit address? (2¹⁵ = 32 kW.)
In some CPU types, instructions are variable-width, so that an instruction which takes two operands is longer than one that takes a single operand, and a self-contained instruction is shorter still, but in the PDP-8, every instruction takes a single 12-bit word. How can a PDP-8 refer to a 12-bit address when the single-word instructions are 12 bits themselves? And how do we get beyond that to 32 kW, which would apparently require a 15-bit address? (2¹⁵ words = 32 kW.)
You may have prior experience with the 16-bit Intel x86 segmentation scheme. If you thought that was a pain, buckle up, it gets wild from here.
You may have prior experience with the [16-bit Intel x86 segmentation scheme](https://en.wikipedia.org/wiki/X86#Segmentation). If you thought writing code to deal with that was a pain, buckle up, it gets wild from here.
# Level 1: Pages
The first memory access level is the “page,” 128 words. That limit comes from the fact that all [PDP-8 memory reference instructions](http://homepage.cs.uiowa.edu/~jones/pdp8/man/mri.html) set aside 7 of their 12 bits for the operand address. That is, if the PDP-8 is executing an instruction in page 0 and it needs to load something from memory address 100₈, it can do so in a single instruction because that address fits into 7 bits.
# Level 2: Fields
To get beyond the page level, you have to use indirect memory accesses. That is, instead of using the 7-bit address to directly refer to the core memory address you're interested in, you store a 12-bit address in one of the core memory locations within the current page and refer indirectly through that location.
For example, let's say you're currently executing in page 0 and need to jump to code that resides at address 234₈, which is in page 1.⁶ You could store the 12-bit value 0234₈ at address 0177₈, then do an indirect jump through page address 177₈.
PDP-8 programmers normally don't have to think too much about such things, even at the assembly language level, because the assembler automatically generates "links" when needed to cross field boundaries like this. Thus, the assembly code looks like a single instruction:
PDP-8 programmers normally don't have to think too much about such things, even at the assembly language level, because the assembler automatically generates "links" when needed to cross field boundaries like this. Thus, the assembly code for what we just described is written as a single assembly language instruction:
JMP 0234
But in reality, this instruction takes two words of core memory: one for the indirect `JMP` instruction, and one for the link.
Since all those links chew into the 4 to 32 kW core limit of any given PDP-8 machine, one of the common games PDP-8 masters play is reusing *instruction* words for target address values and operands to save a word or two.
Since all those links chew into the 4 to 32 kW core limit of any given PDP-8 machine, one of the common games PDP-8 masters play is reusing *instruction and data* words for target address values and operands to save a word or two.
PDP-8 master Rick Murphy taught me one of these games. Instead of saying:
JMP 7600
and taking a "link" penalty, you find a nearby CLA instruction, give it a label in the assembly code, and jump indirectly through that label:
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Thus, when a program is currently executing code in field 0 but wants to address data in field 1, it sets the data field (DF) register to 1, and now all data fetches pull data from field 1. Likewise, to jump to an address in field 1 from field 0, it sets the instruction field (IF) register to 1.
This is also why your PDP-8/I has two sets of 3 switches on the front and a set of indicator lights labeled "Data Field" and "Instruction Field." Together, this gives you a combined 15-bit extended address. A jump or fetch between fields thus takes two instructions, rather than the indirect addressing for in-field operations or the direct addressing of in-page operations. This gives a hierarchy of expense: a diligent PDP-8 programmer tries to keep data and instructions close together and logically bunched to avoid needless page and field transitions.
# Conclusion
I hope you've found that interesting an enlightening. If you would like more on this topic, the various versions of DEC's Small Computer Handbook for the PDP-8 cover this in more detail and take you beyond it, into actual programming of a PDP-8.
I hope you've found this overview interesting and enlightening. If you would like more on this topic, the various versions of DEC's Small Computer Handbook for the PDP-8 cover this in more detail and take you beyond it, into actual programming of a PDP-8:
* The [1967-1968 edition](http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp8/handbooks/SmallComputerHandbook_67-68.pdf) was first published before the PDP-8/I was formally released, so its first drafts must have been written with reference to a pre-production unit.
A telltale of this is that the machines pictured on the front are an original PDP-8 (a.k.a. the "Straight 8") and a PDP-8/S. I have here in my possession a paper copy of a later edition, also labelled as the "1967-1968" edition but with an actual PDP-8/I on the front. You can quickly tell the difference between these two editions by the green background behind the machine, as compared to the orange background behind the older machines. Unfortunately, I'm not aware of a PDF source of the newer edition.
* The 1973 edition for the [PDP-8/e, PDP-8/f, and PDP-8/m](https://archive.org/details/bitsavers_decpdp8hanHandbook1973_79671711) is not entirely relevant to the PDP-8/I we're primarily concerned with here on this web site, but they did refine the tutorial material quite a bit over the earlier editions, so it is sometimes helpful to read the equivalent material in this newer edition when trying to figure something out. Just be aware that not everything applies to a PDP-8/I.
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**Footnotes and Digressions**
1. The PDP-8 does have one programmer-accessible register that isn't an even multiple of 3 bits, the single-bit "link" register, but we won't be talking more about that register in this article. The term "link" in the article does not refer to this register.
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